library ieee;
use ieee.std_logic_1164.all;

entity pract1 is
port(A,B,C,D,E:in std_logic;
	I:out std_logic);
	
end pract1;


architecture bhv of pract1 is
signal AB:std_logic_vector(1 downto 0);
signal ABC:std_logic_vector(2 downto 0);

begin
AB<=A&B;
ABC<=A&b&C;
I <= D when AB="00" else
	 E when ABC="010" else
	 not E when ABC="011" else
	 not D when A='1' else
	 '-';
end bhv;